This invention relates to microprocessors, and more specifically, to programmable output generators.
Processing systems often employ output generators, either as an independent unit or as a peripheral device on a microcontroller. An example of such an independent device is a pulse width modulator for generating a digital timing waveform in response to a triggering signal, such as that described in U.S. Pat. No. 4,719,593 of Threewitt et al. As the demands placed on microprocessors have increased due to the ever larger number of application in which they are employed, such output generators are often employed as peripheral devices within a microcontroller device. An example of such a peripheral embodiment is the high-speed output module described on pp. 8-17 to 8-26 of 8XC196KC/8XC196KD User""s Manual published by Intel, the manufacturer of that particular microcontroller.
As with other peripherals, this arrangement allows for a division of labor with special functions handled by dedicated units while the central processing unit tends to overall device control. When the output of waveform is needed, the CPU can simply supply an enable signal to the output generator rather than producing the waveform itself In this way, the CPU is free to perform other functions while supplying only minimal oversight to the output generator. Besides generating waveforms, a peripheral output generator can also produce other types of events besides generating waveforms, such as starting an analog to digital conversion or generating an interrupt.
As the applications in which microprocessors are used increases in both number and complexity, the desirability of output generators with greater ability and flexibility has correspondingly increased. This is true not just in terms of the need for more complex waveforms, as the processor must interact with a growing variety of increasingly complex devices, but also in the number of different functions which the output generator must perform.
The present invention is a memory mapped programmable output generator, capable of producing events such as creating complex waveforms, triggering analog to digital and digital to analog conversions, and generating processor interrupts. These events are considered high speed since they are timed with relative to a high-speed clock and require minimal processor over head. The event generator may be embodied as either a peripheral to a microcontroller or as a separate circuit.
Programming event data, a next event address pointer, and an event time define an event block in a dual port RAM memory. In the preferred embodiment, a maximum of 64 events may be programmed. When an event begins, the event data and next address bytes are loaded into internal holding buffers and event time is loaded into a countdown timer. Once the programmable output generator is enabled, the first event is loaded into internal operating registers and the countdown timer will immediately begin counting. Once the timer counts to zero, the event will occur and the next address will point to the next event block. The data contained in this next RAM location will then be loaded and be executed at its programmed time. Subsequent events will continue to be loaded and executed until the output generator is either disabled or an event contains a prescribed value of the next address. If the next address is the prescribed value, the output generator will be disabled when this address is sensed and the event itself will not be executed.
In its preferred embodiment, the output generator is a peripheral device on a microcontroller and uses a dedicated programmable reloadable timer which is inaccessible to other blocks. Events are loaded in a serial format, where only one event is active at a given time. These events are sequenced through address pointers associated with each event. Once a given event is completed, the output generator loads the next event from a next address pointer. The dedicated timer loads one event at a time, counts down to zero, then loads the next event time, counts down to zero, and continues in this manner until disabled, either externally by the CPU or internally as a result of a prescribed next address. The output generator utilizes 64 dual port register blocks organized in program memory which is accessible to both the output generator and the top level CPU or microcontroller. In a data output mode, output generator pin events are byte wide thereby allowing up to 8 bits to change during each POG event. Other modes can trigger events in other peripherals or generate an interrupt signal for the CPU.
Additional objects, advantages, and features of the present invention will become apparent form the following description of its preferred embodiments, which description should be taken in conjunction with the accompanying drawings.